The present invention relates to a semiconductor element mounting method for mounting a wafer itself, or semiconductor elements separated from the wafer, onto an interposer which is to be mounted onto a circuit board.
Today, electronic circuit boards have been put into use in every kind of product, and in view of increases in portable equipment, there is a demand for flip-chip mounting methods for mounting circuit-board IC chips as they are naked, other than packaged.
Here is described below a prior-art method for bonding IC chips to a circuit board of electronic equipment.
As shown in FIGS. 20A to 22, a semiconductor element mounting process in which an insulative resin sheet is used as a sealing material for a semiconductor element mounting method has been proposed.
Referring to FIG. 20A, a wafer 101 is sucked onto an equipment first stage 108, planarized and heated to 250° C. from the first stage 108. Thereafter, referring to FIG. 20B, stud bumps 103 are formed from a 25 μm diameter Au wire (made by Mitsubishi Materials Corp.) via a capillary 104 attached to a wire bonding apparatus. Otherwise, bumps may be formed by plating on pads of the wafer 101.
Referring to FIG. 20C, on an interposer 105, an insulative resin sheet 106 containing electrically conductive particles is set in a semiconductor element mounting region. Referring to FIG. 21A, the insulative resin sheet 106 is attached to the interposer 105 by performing heating and pressurization with an attaching tool 107 containing a cartridge heater 108. The heating in this case requires such a temperature that the insulative resin sheet 106 reacts so as to not be cured but softened, thus becoming easier to attach to the interposer 105, where a temperature is normally 60 to 100° C.
Referring to FIGS. 21B and 21C, a film called separator on the insulative resin sheet 106 is separated therefrom, and electrodes on the interposer 105 and the bumps 103 on the wafer are aligned so as to contact each other, respectively. Then, the insulative resin sheet 106 is subjected to a curing reaction through heating and loading with a compression-bonding tool 110 containing a cartridge heater 108a, and thereby compression-bonded. This compression-bonding is performed normally under conditions of 180 to 240° C. and 8 to 30 sec.
Referring to FIG. 22, the wafer 101 compression-bonded to the interposer 105 is divided into chips on a basis of each semiconductor device 126 by using a dicing unit.
For mounting of each semiconductor element chip, normally, an anisotropic conductive film (ACF) formed by mixing conductive particles into an insulative resin sheet has widely been put into practical use as an ACF technique.
Further, it has become achievable to manufacture a semiconductor device simultaneously and easily in short time by performing the foregoing steps.
As shown above, flip chip mounting as shown in the prior art has been proposed and practically used in order to implement downsizing of electrical appliances. However, the flip chip mounting has encountered the following issues.
First, since semiconductor elements are mounted by performing compression-bonding and performing heating and pressurization, chip to chip, productivity is not improved. Therefore, a process has been proposed at a wafer level for improvement of productivity. The process includes steps of forming bumps on electrodes of a wafer, setting an ACF between the wafer and an interposer in contact therewith, curing the ACF by performing heating and pressurization to thereby compression-bond the wafer and the interposer so that electrodes of the wafer and electrodes of the interposer are bonded with each other, and thereafter separating semiconductor elements from one another. However, ACF or other pressure-bonding techniques, like the prior art one, would involve larger amounts of escape of resin of the ACF to peripheral portions of the wafer, while the resin of the ACF could not escape in central portions, thereby making it difficult to achieve uniform bonding at the wafer level.
Second, as formation of stud bumps at a wafer level involves heating a wafer, there would be a large difference in heat history between bump formation for a first semiconductor element and bump formation for a last semiconductor element. In particular, bump formation for earlier numbers of order of a bump formation sequence would require a longer heating time, which would promote formation of alloy layers between this semiconductor element and Au bumps. This would result in lowered bonding strengths of bumps on electrodes of semiconductor elements.
Third, during stud bump formation on a semiconductor element, there is a possibility that electrodes of semiconductor elements, such as Al, would be exposed, which might in turn cause corrosion of these semiconductor-element electrodes due to moisture absorption after assembling of a semiconductor device.
Fourth, at present, since marking of a first pin or the like is applied to one surface of a semiconductor element opposite to its semiconductor-element surface for each chip of semiconductor devices, productivity is not improved.
Fifth, during marking at a wafer level, there is a difficulty in recognizing a positional relationship between a semiconductor-element surface and a semiconductor-element opposing surface. In this regard, though a through hole may be provided in semiconductor elements during etching or another process to show a front-and-rear surface positional relationship, this would cause an increase in cost.
Sixth, in the ACF process, which includes attaching an ACF to an interposer and thereafter mounting semiconductor elements, supply of insulative sealing resin for semiconductor elements is performed on a basis of each semiconductor element chip, which would result in lower productivity. Moreover, attaching the ACF arbitrarily to a specified place of the interposer poses a complexity for mass-production equipment. Furthermore, in a case where a plurality of semiconductor elements are mounted on one interposer, a plurality of sizes of ACFs need to be prepared in terms of process, which would lead to an increase in cost as well as a complexity in mass-production control.
Seventh, in a case of a semiconductor device made up by stacking a plurality of semiconductor elements, using as a stacking technique an ACF or other pressure-bonding technique involving pressurization and heating would cause a lower-side wafer to be bent during the pressurization, which would result in insufficient electrical bonding between a lower-layer wafer and an upper-layer wafer.
Eighth, in a case of a semiconductor device made up by stacking a plurality of semiconductor elements, cutting a wafer into chips after wafer stacking might incur defects or cracks of the semiconductor elements due to orientation differences in semiconductor crystal planes between upper and lower layers.
Among various issues as described above, in particular, the greatest issue is that productivity improvement cannot be achieved because of a process by which semiconductor elements are compression-bonded and subjected to heat and pressurization on a chip basis for element mounting.
Accordingly, an object of the present invention is to provide a semiconductor element mounting method capable of high productivity.